Typically, many ICs are driven by clocks for performing various operations in large digital circuits that may include logic gates, flip-flops (FFs), input/output buffers, and others. Switching activity of these large digital circuits may result in switching components included in these large digital circuits drawing an undesirable, large periodic peak current, especially when the switching activity is concurrently triggered by a leading (or trailing edge) of the clock. The large periodic peak current may generate an IR drop in a local power supply network providing power to the ICs. This IR drop may result in degraded timing performance of the ICs. In addition, in an IC design that includes mixed (analog and digital) signals, a large periodic peak current (and the resulting IR drop) may generate undesirable interference signals in mixed signal processing circuits that may degrade the performance of the IC.
Traditional techniques such as placing local decoupling capacitors (decaps) to filter the interference signals may be used to mitigate the effects of peak currents on the performance of the IC. However, many of these techniques may also require a significant increase in silicon area required to fabricate the IC. In addition, larger sized decaps may also increase leakage current.